The power amplifier (PA) is usually the most power hungry block in a wideband radio device, which typically operates at mm-wave frequency range, e.g. IEEE802.11ad standard at 60 GHz. In addition, phased array antennas are typically employed to overcome the high signal losses at this frequency range. However, the cost of the analog frontend systems increases in proportion to the number of antenna paths. This will drastically increase the power consumption, especially the share of the most power hungry PA. Improving the power efficiency of a radio transmitter is therefore critical in reducing the power cost of the wideband radio transmitters, which for example, are applied for high data rate short-range portable applications that require minimal power consumption for longer battery lifetime and high data rate backhaul systems that transmit with high output powers for longer range communication.
In such applications, in addition, most PAs operate in class-A linear mode due to the use of variable envelope modulations that are required for high data rates and high spectral efficiency. This causes the typical PA power efficiency of less than 5%, although records up to 30% could be achieved. In order to improve the PA power efficiency, the PA needs to work in its nonlinear region to utilize the peak efficiency. The radio employing a polar architecture is an approach that allows the PA to operate in saturation without the need for duplicating the signal path or using power combiners. In polar transmitters, the quadrature, I and Q, signals are converted to a phase (PH) and an amplitude (AM) signals, wherein the PH signal is used as input for the PA and AM is applied to the PA through a separate modulation path.
In conventional polar radio architectures, the conversion of quadrature to polar signals is typically done in radio frequency (RF) domain, wherein the amplitude (AM) signal is extracted from the RF modulated signal by an amplitude detection circuit, such as an envelope detector, operating at RF frequency. The phase signal is extracted by an RF limiter circuit, which introduces extra nonlinearity and bandwidth limitations. The phase signal is then fed to the input of the PA, while the amplitude signal is used to modulate the supply voltage of the PA. Such polar architectures, however, suffer from low power efficiency, high nonlinearity and bandwidth limitations. In recent papers, for example, the paper of In-Seok Jung, Yong-Bin Kim, “A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA Transmitter,” IEEE Transactions on Industrial Electronics, vol. 59, no. 2, pp. 1154, 1160, Febuary 2012, and the paper of Chung-Chun Chen et. al., “Polar transmitter for wireless communication system,” Proceedings of 2005 International Symposium on Intelligent Signal Processing and Communication Systems, pp. 613, 616, 13-16 Dec. 2005, propose a digital polar modulator system employing a CORDIC processor for the conversion of the digital quadrature, in-phase (I) and quadrature (Q), signals into polar, i.e. amplitude and phase, signals. The phase signal is used to modulate a local oscillation signal. Thus, the conversion to polar signals is done in digital domain at baseband frequency instead of in analog domain at RF frequency.
Although employing a digital signal processor (DSP), such as a CORDIC processor, for the quadrature-to-polar conversion, the design of the digital frontend system of a polar radio for wideband applications, is still very challenging, as the digital front-end system has to work at a very high speed (e.g. at mm-waves in the range of GHz). This generates a bottleneck in the power budget in such polar transmitters where minimal power consumption and long battery lifetime is highly important. Power-efficient implementation of a digital frontend system is surely critical for wideband radio transmitters.